In the semiconductor industry, fuse elements are widely used in integrated circuits for a variety of purposes, such as improving manufacturing yield or customizing a generic integrated circuit. For example, by programming fuses to replace defective circuits on a chip with redundant circuits on the same chip, manufacturing yields can be significantly increased. Replacing defective circuits is especially useful for improving manufacturing yield of the memory chips since memory chips consist of many identical memory cells and cell groups. By selectively blowing fuses within an integrated circuit that has multiple potential uses, a generic integrated circuit design may be economically manufactured and adapted to a variety of custom uses.
Generally, there are two different methods to disconnect fuses. In one method, the disconnection is carried out by the action of a laser beam, and the fuse is referred to as a laser fuse. In order to zap a laser fuse formed in a chip, an opening in a passivation layer is typically formed allowing the laser direct access to the fuse metal link that is to be cut. Thus, laser fuses are preferably formed close to the surface of a chip in order to avoid cutting deep openings in the passivation layer, which may increase process complexity and decrease the laser repair rate. However, forming fuse elements close to the surface of a chip casts security concerns on protecting the intellectual property of a designed integrated circuit (IC), for example.
In another method, the disconnection of a fuse is carried out by electrical destruction resulting from the electromigration produced by an electrical current. Such a fuse is referred as an electrical fuse, or e-fuse. FIG. 1A illustrates a conventional e-fuse 10 that can be formed in a deep process layer of a chip, thus providing the desired protection of the intellectual property of a designed IC. E-fuse 10 comprises a polysilicon (poly) strip 5 that is formed and patterned over a semiconductor substrate (not shown). Poly stripe 5 is un-doped or lightly-doped, thus exhibiting a high electrical resistance. Formed atop poly stripe 5 is a silicide layer 7 that has a low resistance. The two ends of e-fuse 10 are coupled to the anode and the cathode of a predetermined programming potential, respectively, through conductive features, such as contact/via 3. Before e-fuse 10 is burned out, its resistance is mainly determined by the resistance of the silicide layer 7.
FIG. 1B shows e-fuse 10 when a predetermined programming potential is applied across its ends. The electrical current passes e-fuse 10 primarily through silicide layer 7 due to its low resistance. A known phenomenon named electromigration causes silicide layer 7 to accumulate and agglomerate at the anode end, forming silicide accumulation 9, and to create an electrical discontinuity in e-fuse 10. Therefore, after e-fuse 10 is programmed, the resistance of e-fuse 10 is mainly determined by poly strip 5 so that the resistance is significantly increased. Ideally, a very large, close-to-open resistance of e-fuse 10 is achieved after programming in order to obtain a large IC design window.
While the trend of device feature size scaling continues in advanced technology, the structure of a conventional e-fuse and the described approach of programming a conventional e-fuse have become increasingly problematic in a few ways. Firstly, due to the size shrinkage of an e-fuse in advanced technology, the post-programming resistance of an e-fuse will not be large enough, and the difference between a pre-programming e-fuse resistance and a post-programming e-fuse resistance will become vague. This problem may lead to a significantly lowered repairable rate and reduced IC design window. Secondly, as e-fuse dimension decreases in advanced technology, a detrimental effect known as poly thermal rupture is increasingly prone to occur due to the increased current density on a shrunk poly stripe of an e-fuse. Poly thermal rupture may cause permanent physical damage on a poly stripe, which may, in turn, cast serious reliability risk during the lifetime of an e-fuse.
FIG. 2A illustrates another known e-fuse 20 that may be formed in a deep process layer of a chip. E-fuse 20 comprises top conductive layer 11, bottom conductive layer 15, and contact 13 coupled in between. In programming e-fuse 20, top conductive layer 11 and bottom conductive layer 15 are coupled to the cathode and the anode of a predetermined programming potential, respectively. Similarly, the effect of electromigration causes the metal material of contact 13 to accumulate and agglomerate at the anode end of e-fuse 20, forming contact metal accumulation 19. This results in the depletion of the metal material of contact 13, leaving void 17 in the region of contact 13. The void thus created leads to a significantly increased fuse resistance. A resultant structure of e-fuse 20 after programming is shown in FIG. 2B.
As a consequence, the so-called pure contact fuse described above is susceptible to an effect known as metal reflow. The high current density in advanced technology may melt the conductive material used for the top conductive layer 11 and may cause the conductive material of conductive layer 11 to refill the void 17 created during the fuse programming process. The undesired refill process may nullify a pre-programmed e-fuse and causes serious reliability concerns in an IC. This detrimental effect is prone to occur when low melting-point metal materials, such as copper (Cu) or aluminum (AL), are used for top conductive layer 11.